Publication detail

DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION

A. S. KUNCHEVA, L. FUJCIK, T. MOUGEL, B. DONCHEV, M. HRISTOV

Original Title

DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION

English Title

DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION

Type

conference paper

Language

en

Original Abstract

This paper describes steps involved in a VHDL design of digital decimation filter for multibit sigma-delta modulator. Parameters of decimation filter are derived from the specification of the multibit SD modulator with two-step quantization architecture. Using Matlabtool it is possible to find the filter order, the required quantizationlevel for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The design is programmed and tested on a Xilinx FPGA Spartan 3 XC3S200-5FT256.

English abstract

This paper describes steps involved in a VHDL design of digital decimation filter for multibit sigma-delta modulator. Parameters of decimation filter are derived from the specification of the multibit SD modulator with two-step quantization architecture. Using Matlabtool it is possible to find the filter order, the required quantizationlevel for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The design is programmed and tested on a Xilinx FPGA Spartan 3 XC3S200-5FT256.

Keywords

decimation filter, programmable logic device

RIV year

2006

Released

01.01.2006

Location

Gdynia

ISBN

83-922632-1-9

Book

Proceedings of the International Conference, Mixed Design of Integrated Circuits and Systems

Pages from

83

Pages to

86

Pages count

4

BibTex


@inproceedings{BUT22118,
  author="Lukáš {Fujcik} and Thibault {Mougel}",
  title="DESIGN OF DECIMATION FILTER FOR MULTIBIT SIGMA-DELTA MODULATOR WITH TWO-STEP QUANTIZATION",
  annote="This paper describes steps involved in a VHDL design of digital decimation filter for multibit sigma-delta modulator. Parameters of decimation filter are derived from the specification of the multibit SD modulator with two-step quantization architecture. Using Matlabtool it is possible to find the filter order, the required quantizationlevel for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The design is programmed and tested on a Xilinx FPGA Spartan 3 XC3S200-5FT256.",
  booktitle="Proceedings of the International Conference, Mixed Design of Integrated Circuits and Systems",
  chapter="22118",
  year="2006",
  month="january",
  pages="83",
  type="conference paper"
}