Publication detail

The New Low Power 10-bit Pipelined ADC Using Novel Background Calibration Technique

HÁZE, J. VRBA, R.

Original Title

The New Low Power 10-bit Pipelined ADC Using Novel Background Calibration Technique

English Title

The New Low Power 10-bit Pipelined ADC Using Novel Background Calibration Technique

Type

conference paper

Language

en

Original Abstract

The paper deals with new background calibration technique, which is utilized in new 10-bit low power pipelined ADC. The switched-capacitor approach is used in designed ADC as well. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operational-amplifier (op-amp) sharing technique was used to decrease the power usage as well as capacitor scaling approach. To avoid the clock feedthrough from digital part through the switches, the fully differential circuitry was utilized. The operational transkonductance amplifier (OTA) was used in design instead of op-amp. The power consumption of the OTA and other analog parts were taken into account in design procedure. The finite op-amp dc gain problem is solved in digital-domain using background calibration. The capacitor mismatch and op-amp offset are compensated in the same manner.

English abstract

The paper deals with new background calibration technique, which is utilized in new 10-bit low power pipelined ADC. The switched-capacitor approach is used in designed ADC as well. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operational-amplifier (op-amp) sharing technique was used to decrease the power usage as well as capacitor scaling approach. To avoid the clock feedthrough from digital part through the switches, the fully differential circuitry was utilized. The operational transkonductance amplifier (OTA) was used in design instead of op-amp. The power consumption of the OTA and other analog parts were taken into account in design procedure. The finite op-amp dc gain problem is solved in digital-domain using background calibration. The capacitor mismatch and op-amp offset are compensated in the same manner.

Keywords

Pipelined ADC, switched-capacitors, background calibration, portable devices

RIV year

2006

Released

01.01.2006

Publisher

IEEE Computer Society

Location

Kuala Lumpur, Malaysia

ISBN

0-7695-2500-8

Book

Third IEEE International Workshop on Electronic Design, Test and Applications

Edition number

1

Pages from

340

Pages to

344

Pages count

5

BibTex


@inproceedings{BUT21206,
  author="Jiří {Háze} and Radimír {Vrba}",
  title="The New Low Power 10-bit Pipelined ADC Using Novel Background Calibration Technique",
  annote="The paper deals with new background calibration technique, which is utilized in new 10-bit low power pipelined ADC. The switched-capacitor approach is used in designed ADC as well. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operational-amplifier (op-amp) sharing technique was used to decrease the power usage as well as capacitor scaling approach. To avoid the clock feedthrough from digital part through the switches, the fully differential circuitry was utilized. The operational transkonductance amplifier (OTA) was used in design instead of op-amp. The power consumption of the OTA and other analog parts were taken into account in design procedure. The finite op-amp dc gain problem is solved in digital-domain using background calibration. The capacitor mismatch and op-amp offset are compensated in the same manner.",
  address="IEEE Computer Society",
  booktitle="Third IEEE International Workshop on Electronic Design, Test and Applications",
  chapter="21206",
  institution="IEEE Computer Society",
  year="2006",
  month="january",
  pages="340",
  publisher="IEEE Computer Society",
  type="conference paper"
}