Publication detail

BIT ERROR RATE TESTER BASED ON FPGA STRUCTURE

BRADÁČ, Z., VALACH, S.

Original Title

BIT ERROR RATE TESTER BASED ON FPGA STRUCTURE

English Title

BIT ERROR RATE TESTER BASED ON FPGA STRUCTURE

Type

conference paper

Language

en

Original Abstract

This article describes the implementation of a RocketIO bit-error rate tester (BERT) on the DSP custom board FD64x. The BER test is aimed at the serial link between two transceivers placed in the Virtex-II Pro FPGA. The tester module generating PRBS pattern, verifying received data and counting bit errors.

English abstract

This article describes the implementation of a RocketIO bit-error rate tester (BERT) on the DSP custom board FD64x. The BER test is aimed at the serial link between two transceivers placed in the Virtex-II Pro FPGA. The tester module generating PRBS pattern, verifying received data and counting bit errors.

RIV year

2006

Released

01.02.2006

Publisher

VUT Brno

Location

Brno

ISBN

80-214-3130-

Book

Proceedings of IFAC WORKSHOP on Programmable Devices and Embedded Systems PDeS2003

Pages from

433

Pages to

436

Pages count

4

BibTex


@inproceedings{BUT19450,
  author="Zdeněk {Bradáč} and Soběslav {Valach}",
  title="BIT ERROR RATE TESTER BASED ON FPGA STRUCTURE",
  annote="This article describes the implementation of a RocketIO bit-error rate tester
(BERT) on the DSP custom board FD64x. The BER test is aimed at the serial link
between two transceivers placed in the Virtex-II Pro FPGA. The tester module generating
PRBS pattern, verifying received data and counting bit errors.",
  address="VUT Brno",
  booktitle="Proceedings of IFAC WORKSHOP on Programmable Devices and Embedded Systems PDeS2003",
  chapter="19450",
  institution="VUT Brno",
  year="2006",
  month="february",
  pages="433",
  publisher="VUT Brno",
  type="conference paper"
}