Publication detail

Design of the Special Fast Reconfigurable Chip Using Common FPGA

SEKANINA, L., RŮŽIČKA, R.

Original Title

Design of the Special Fast Reconfigurable Chip Using Common FPGA

English Title

Design of the Special Fast Reconfigurable Chip Using Common FPGA

Type

conference paper

Language

en

Original Abstract

Some applications require chips with fast partial reconfiguration. These requirements are traditionally satisfied by a special chip design, but it is usually a very expensive solution. This paper describes a new approach. Special fast partially reconfigurable chip is implemented with a common FPGA. The format of the configuration bit stream is suggested and optimized according to the given task. Result chip offers many good properties, but some problems with scalability can appear.

English abstract

Some applications require chips with fast partial reconfiguration. These requirements are traditionally satisfied by a special chip design, but it is usually a very expensive solution. This paper describes a new approach. Special fast partially reconfigurable chip is implemented with a common FPGA. The format of the configuration bit stream is suggested and optimized according to the given task. Result chip offers many good properties, but some problems with scalability can appear.

Keywords

reconfigurable circuits, evolvable hardware

Released

01.01.2000

Publisher

unknown

Location

Smolenice

ISBN

80-968320-3-4

Book

Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000

Pages from

161

Pages to

168

Pages count

8

URL

Documents

BibTex


@inproceedings{BUT17637,
  author="Lukáš {Sekanina} and Richard {Růžička}",
  title="Design of the Special Fast Reconfigurable Chip Using Common FPGA",
  annote="Some applications require chips with fast partial reconfiguration. These requirements are traditionally satisfied by a special chip design, but it is usually a very expensive solution. This paper describes a new approach. Special fast partially reconfigurable chip is implemented with a common FPGA. The format of the configuration bit stream is suggested and optimized according to the given task. Result chip offers many good properties, but some problems with scalability can appear.",
  address="unknown",
  booktitle="Proc. of Design and Diagnostics of Electronic Circuits and Systems - IEEE DDECS'2000",
  chapter="17637",
  institution="unknown",
  year="2000",
  month="january",
  pages="161--168",
  publisher="unknown",
  type="conference paper"
}