Publication detail

On Routine Implementation of Virtual Evolvable Devices Using COMBO6

SEKANINA, L., FRIEDL, Š.

Original Title

On Routine Implementation of Virtual Evolvable Devices Using COMBO6

English Title

On Routine Implementation of Virtual Evolvable Devices Using COMBO6

Type

conference paper

Language

en

Original Abstract

This paper introduces an approach showing that a complete implementation of a digital evolvable hardware system can automatically be created from a high-level specification.
The approach generates the implementation of a virtual reconfigurable circuit and  evolutionary algorithm independently of a target platform, i.e. as a soft IP core. The method is evaluated on the development of two high-performance evolvable systems that are utilized for fast evolutionary design of small combinational circuits, such as 3x3-bit multipliers. The COMBO6 card is employed for these experiments.

English abstract

This paper introduces an approach showing that a complete implementation of a digital evolvable hardware system can automatically be created from a high-level specification.
The approach generates the implementation of a virtual reconfigurable circuit and  evolutionary algorithm independently of a target platform, i.e. as a soft IP core. The method is evaluated on the development of two high-performance evolvable systems that are utilized for fast evolutionary design of small combinational circuits, such as 3x3-bit multipliers. The COMBO6 card is employed for these experiments.

Keywords

evolvable hardware, evolutionary circuit design, COMBO6

RIV year

2004

Released

29.06.2004

Publisher

IEEE Computer Society Press

Location

Los Alamitos

ISBN

0-7695-2145-2

Book

Proc. of the 2004 NASA/DoD Conference on Evolvable Hardware

Pages from

63

Pages to

70

Pages count

8

URL

Documents

BibTex


@inproceedings{BUT17342,
  author="Lukáš {Sekanina} and Štěpán {Friedl}",
  title="On Routine Implementation of Virtual Evolvable Devices Using COMBO6",
  annote="This paper introduces an approach showing that a complete implementation of a digital evolvable hardware system can automatically be created from a high-level specification. 
The approach generates the implementation of a virtual reconfigurable circuit and  evolutionary algorithm independently of a target platform, i.e. as a soft IP core. The method is evaluated on the development of two high-performance evolvable systems that are utilized for fast evolutionary design of small combinational circuits, such as 3x3-bit multipliers. The COMBO6 card is employed for these experiments.
", address="IEEE Computer Society Press", booktitle="Proc. of the 2004 NASA/DoD Conference on Evolvable Hardware", chapter="17342", institution="IEEE Computer Society Press", year="2004", month="june", pages="63--70", publisher="IEEE Computer Society Press", type="conference paper" }