Publication detail

Formal Approach to Synthesis of a Test Controller

RŮŽIČKA, R., TUPEC, P.

Original Title

Formal Approach to Synthesis of a Test Controller

English Title

Formal Approach to Synthesis of a Test Controller

Type

conference paper

Language

en

Original Abstract

In the paper, a method for formal construction of a test controller of the RT level digital circuit is presented. As input, a digital circuit structure at RT level designed using any DfT technique is assumed. The proposed method enables to create a Finite State Machine with output, which can control all enable, address and clock inputs of circuit elements during the test application process. It is assumed that test patterns are inserted to circuit primary input ports and transferred through the circuit structure to selected points inside the circuit, to which they must be applied. Responses to these test patterns must then be transferred outside of the circuit and analyzed. Transfers of such diagnostic data are controlled by the test controller. Formal tools and approaches are used. The main advantage of formally described methods is that all processes are easily provable and no large evaluation of proposed methods on benchmark circuits is necessary.

English abstract

In the paper, a method for formal construction of a test controller of the RT level digital circuit is presented. As input, a digital circuit structure at RT level designed using any DfT technique is assumed. The proposed method enables to create a Finite State Machine with output, which can control all enable, address and clock inputs of circuit elements during the test application process. It is assumed that test patterns are inserted to circuit primary input ports and transferred through the circuit structure to selected points inside the circuit, to which they must be applied. Responses to these test patterns must then be transferred outside of the circuit and analyzed. Transfers of such diagnostic data are controlled by the test controller. Formal tools and approaches are used. The main advantage of formally described methods is that all processes are easily provable and no large evaluation of proposed methods on benchmark circuits is necessary.

Keywords

Testability, Test Controller, Automata, I path

RIV year

2004

Released

24.05.2004

Publisher

IEEE Computer Society

Location

Los Alamitos, California

ISBN

0-7695-2125-8

Book

Proceedings of Eleventh International Conference and Workshop on the Engineering of Computer-Based Systems

Pages from

348

Pages to

355

Pages count

8

Documents

BibTex


@inproceedings{BUT17129,
  author="Richard {Růžička} and Pavel {Tupec}",
  title="Formal Approach to Synthesis of a Test Controller",
  annote="In the paper, a method for formal construction of a test controller of the RT level digital circuit is presented. As input, a digital circuit structure at RT level designed using any DfT technique is assumed. The proposed method enables to create a Finite State Machine with output, which can control all enable, address and clock inputs of circuit elements during the test application process. It is assumed that test patterns are inserted to circuit primary input ports and transferred through the circuit structure to selected points inside the circuit, to which they must be applied. Responses to these test patterns must then be transferred outside of the circuit and analyzed. Transfers of such diagnostic data are controlled by the test controller. Formal tools and approaches are used. The main advantage of formally described methods is that all processes are easily provable and no large evaluation of proposed methods on benchmark circuits is necessary.",
  address="IEEE Computer Society",
  booktitle="Proceedings of Eleventh International Conference and Workshop on the Engineering of Computer-Based Systems",
  chapter="17129",
  institution="IEEE Computer Society",
  year="2004",
  month="may",
  pages="348--355",
  publisher="IEEE Computer Society",
  type="conference paper"
}