Publication detail

Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study

PODIVÍNSKÝ, J. ČEKAN, O. KRČMA, M. BURGET, R. HRUŠKA, T. KOTÁSEK, Z.

Original Title

Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study

English Title

Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study

Type

conference paper

Language

en

Original Abstract

Almost every today's electronic devices are equipped with a processor. Different applications require and depend on different properties of a  processor. For example, the fast growing field of Internet of Things depends on a long operation time of the devices when powered with batteries. Using a general purpose processors has proved ineffective which led to growing usage of Application-Specific Instruction-Set processors (ASIPs) which can be optimized to specific applications using different modifications of their properties (such as the number of registers, cache sizes, instruction set modifications, etc.). A suitable processor configuration can be hand-picked by a designer or by an automatic tool. Such a tool was developed in our previous research. It is able to find a set of Pareto-optimal processor configurations for a  specific application which can be a significant help in a device design. The cost of the design process can be cut significantly when a  processor is used in multiple designs. The gal of this paper is to introduce a tool able to find a suitable processor configuration for multiple application by constructing a compromise Pareto-optimal frontier of a processor configurations. The paper describes this problem on a theoretical level as well as it introduces a practical implementation and experimental evaluation of constructing a compromise Pareto frontier of a processor configurations for a set of applications. The experiments are based on a parameterizable RISC-V processor.

English abstract

Almost every today's electronic devices are equipped with a processor. Different applications require and depend on different properties of a  processor. For example, the fast growing field of Internet of Things depends on a long operation time of the devices when powered with batteries. Using a general purpose processors has proved ineffective which led to growing usage of Application-Specific Instruction-Set processors (ASIPs) which can be optimized to specific applications using different modifications of their properties (such as the number of registers, cache sizes, instruction set modifications, etc.). A suitable processor configuration can be hand-picked by a designer or by an automatic tool. Such a tool was developed in our previous research. It is able to find a set of Pareto-optimal processor configurations for a  specific application which can be a significant help in a device design. The cost of the design process can be cut significantly when a  processor is used in multiple designs. The gal of this paper is to introduce a tool able to find a suitable processor configuration for multiple application by constructing a compromise Pareto-optimal frontier of a processor configurations. The paper describes this problem on a theoretical level as well as it introduces a practical implementation and experimental evaluation of constructing a compromise Pareto frontier of a processor configurations for a set of applications. The experiments are based on a parameterizable RISC-V processor.

Keywords

Pareto optimization, Pareto frontier, processor optimization, ASIP.

Released

27.06.2019

Publisher

Czech Technical University

Location

Roztoky u Prahy

ISBN

978-80-01-06607-2

Book

Proceedings of the 7th Prague Embedded Systems Workshop

Edition

NEUVEDEN

Edition number

NEUVEDEN

Pages from

20

Pages to

21

Pages count

2

URL

Documents

BibTex


@inproceedings{BUT162466,
  author="Jakub {Podivínský} and Ondřej {Čekan} and Martin {Krčma} and Radek {Burget} and Tomáš {Hruška} and Zdeněk {Kotásek}",
  title="Multidimensional Pareto Frontiers Intersection: Processor Optimization Case Study",
  annote="Almost every today's electronic devices are equipped with a processor. Different
applications require and depend on different properties of a  processor. For
example, the fast growing field of Internet of Things depends on a long operation
time of the devices when powered with batteries. Using a general purpose
processors has proved ineffective which led to growing usage of
Application-Specific Instruction-Set processors (ASIPs) which can be optimized to
specific applications using different modifications of their properties (such as
the number of registers, cache sizes, instruction set modifications, etc.).
A suitable processor configuration can be hand-picked by a designer or by an
automatic tool. Such a tool was developed in our previous research. It is able to
find a set of Pareto-optimal processor configurations for a  specific application
which can be a significant help in a device design. The cost of the design
process can be cut significantly when a  processor is used in multiple designs.
The gal of this paper is to introduce a tool able to find a suitable processor
configuration for multiple application by constructing a compromise
Pareto-optimal frontier of a processor configurations. The paper describes this
problem on a theoretical level as well as it introduces a practical
implementation and experimental evaluation of constructing a compromise Pareto
frontier of a processor configurations for a set of applications. The experiments
are based on a parameterizable RISC-V processor.",
  address="Czech Technical University",
  booktitle="Proceedings of the 7th Prague Embedded Systems Workshop",
  chapter="162466",
  edition="NEUVEDEN",
  howpublished="online",
  institution="Czech Technical University",
  year="2019",
  month="june",
  pages="20--21",
  publisher="Czech Technical University",
  type="conference paper"
}