Publication detail

CHIRP SINE GENERATION ON FIX-POINT FPGA

KUNZ, J. BENEŠ, P.

Original Title

CHIRP SINE GENERATION ON FIX-POINT FPGA

English Title

CHIRP SINE GENERATION ON FIX-POINT FPGA

Type

abstract

Language

en

Original Abstract

This paper deals with a logarithmic and a linear chirp sine generation on a fix-point FPGA. Basic overview of the logarithmic chirp sine signal and its usage is provided. Then, methods of software signal generation are described and their pros and cons are mentioned. A point-to-point method, which is able to generate both signals mentioned above, is selected for implementation. Its limitations, such as resolution limit, number wrapping and result rounding, are revealed. Moreover, a formula for maximal error caused by fix-point length, signal frequency, sampling frequency and signal parameters is presented. Therefore, the parameters for a maximal error can be calculated, so the implementation can be modified to fulfil a specific application needs. Furthermore, parameters are calculated to fulfil vibration testing criteria according to IEC:60068-2-6, then the method is implemented to a fix-point FPGA and used for a vibration testing.

English abstract

This paper deals with a logarithmic and a linear chirp sine generation on a fix-point FPGA. Basic overview of the logarithmic chirp sine signal and its usage is provided. Then, methods of software signal generation are described and their pros and cons are mentioned. A point-to-point method, which is able to generate both signals mentioned above, is selected for implementation. Its limitations, such as resolution limit, number wrapping and result rounding, are revealed. Moreover, a formula for maximal error caused by fix-point length, signal frequency, sampling frequency and signal parameters is presented. Therefore, the parameters for a maximal error can be calculated, so the implementation can be modified to fulfil a specific application needs. Furthermore, parameters are calculated to fulfil vibration testing criteria according to IEC:60068-2-6, then the method is implemented to a fix-point FPGA and used for a vibration testing.

Keywords

Linear Chirp Sine, Logarithm Chirp Sine, FPGA, Fix-point, Generation

Released

09.04.2019

Location

Brno

ISBN

978-80-214-5733-1

Book

ERIN 2019

Edition

1

Edition number

1

Pages from

29

Pages to

29

Pages count

1

Documents

BibTex


@misc{BUT160685,
  author="Jan {Kunz} and Petr {Beneš}",
  title="CHIRP SINE GENERATION ON FIX-POINT FPGA",
  annote="This paper deals with a logarithmic and a linear chirp sine generation on a fix-point FPGA. Basic overview of the logarithmic chirp sine signal and its usage is provided. Then, methods of software signal generation are described and their pros and cons are mentioned. A point-to-point method, which is able to generate both signals mentioned above, is selected for implementation. Its limitations, such as resolution limit, number wrapping and result rounding, are revealed. Moreover, a formula for maximal error caused by fix-point length, signal frequency, sampling frequency and signal parameters is presented. Therefore, the parameters for a maximal error can be calculated, so the implementation can be modified to fulfil a specific application needs. Furthermore, parameters are calculated to fulfil vibration testing criteria according to IEC:60068-2-6, then the method is implemented to a fix-point FPGA and used for a vibration testing.",
  booktitle="ERIN 2019",
  chapter="160685",
  edition="1",
  howpublished="print",
  year="2019",
  month="april",
  pages="29--29",
  type="abstract"
}