Publication detail

New VHDL Design of Decimation Filter for Sigma-Delta Modulator

L. Fujcik, A. S. Kuncheva, T. Mougel, R. Vrba

Original Title

New VHDL Design of Decimation Filter for Sigma-Delta Modulator

English Title

New VHDL Design of Decimation Filter for Sigma-Delta Modulator

Type

conference paper

Language

en

Original Abstract

This paper describes steps involved in a new VHDL design of a decimation filter for a sigma-delta modulator. Parameters of decimation filter are derived from the specifications of the overall modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 microm technology.

English abstract

This paper describes steps involved in a new VHDL design of a decimation filter for a sigma-delta modulator. Parameters of decimation filter are derived from the specifications of the overall modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 microm technology.

Keywords

VHDL, Design, Decimation Filter, Sigma-Delta Modulator

RIV year

2005

Released

01.01.2005

Publisher

Malaysia

Location

Kuala Lumpur, Malaysie

ISBN

0-7803-9371-6

Book

International Conference on Sesnsor and New Techniques in Pharmaceutical and Biomedical Research

Pages from

32

Pages to

35

Pages count

4

BibTex


@inproceedings{BUT15247,
  author="Lukáš {Fujcik} and Thibault {Mougel} and Radimír {Vrba}",
  title="New VHDL Design of Decimation Filter for Sigma-Delta Modulator",
  annote="This paper describes steps involved in a new VHDL design of a decimation filter for a sigma-delta modulator. Parameters of decimation filter are derived from the specifications of the overall modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 microm technology.",
  address="Malaysia",
  booktitle="International Conference on Sesnsor and New Techniques in Pharmaceutical and Biomedical Research",
  chapter="15247",
  institution="Malaysia",
  year="2005",
  month="january",
  pages="32",
  publisher="Malaysia",
  type="conference paper"
}