Publication detail

An Energy-Efficient DAC Switching Algorithm Based on Charge Recycling Method for SAR ADCs

AKBARI, M. HASHEMIPOUR, O. KHATEB, F. MORADI, F.

Original Title

An Energy-Efficient DAC Switching Algorithm Based on Charge Recycling Method for SAR ADCs

English Title

An Energy-Efficient DAC Switching Algorithm Based on Charge Recycling Method for SAR ADCs

Type

journal article in Web of Science

Language

en

Original Abstract

This letter configures a successive approximation register (SAR) analog-to-digital converter (ADC) based on a new switching algorithm with efficient energy consumption. The proposed switching algorithm applies the same reference voltage to the bottom plates of all capacitors in each capacitor array to drain no energy through capacitors. In addition to a 100 % energy saving in the switched-capacitor digital-to-analog converter (DAC) block, configuration of an N-bit SAR ADC shows a 50 % capacitor area reduction in comparison with the conventional SAR ADC.

English abstract

This letter configures a successive approximation register (SAR) analog-to-digital converter (ADC) based on a new switching algorithm with efficient energy consumption. The proposed switching algorithm applies the same reference voltage to the bottom plates of all capacitors in each capacitor array to drain no energy through capacitors. In addition to a 100 % energy saving in the switched-capacitor digital-to-analog converter (DAC) block, configuration of an N-bit SAR ADC shows a 50 % capacitor area reduction in comparison with the conventional SAR ADC.

Keywords

Energy-efficient, Switching algorithm, SAR ADC, Capacitor array, Comparator

Released

02.11.2018

Publisher

ELSEVIER SCI LTD

Location

England

Pages from

29

Pages to

35

Pages count

7

URL

BibTex


@article{BUT150685,
  author="Meysam {Akbari} and Omid {Hashemipour} and Fabian {Khateb} and Farshad {Moradi}",
  title="An Energy-Efficient DAC Switching Algorithm Based on Charge Recycling Method for SAR ADCs",
  annote="This letter configures a successive approximation register (SAR) analog-to-digital converter (ADC) based on a new switching algorithm with efficient energy consumption. The proposed switching algorithm applies the same reference voltage to the bottom plates of all capacitors in each capacitor array to drain no energy through capacitors. In addition to a 100 % energy saving in the switched-capacitor digital-to-analog converter (DAC) block, configuration of an N-bit SAR ADC shows a 50 % capacitor area reduction in comparison with the conventional SAR ADC.",
  address="ELSEVIER SCI LTD",
  chapter="150685",
  doi="10.1016/j.mejo.2018.10.011",
  howpublished="print",
  institution="ELSEVIER SCI LTD",
  number=", IF: 1.322",
  volume="82",
  year="2018",
  month="november",
  pages="29--35",
  publisher="ELSEVIER SCI LTD",
  type="journal article in Web of Science"
}