Publication detail

A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

KULEJ, T. KHATEB, F. FERREIRA, L.

Original Title

A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS

Type

journal article in Web of Science

Language

English

Original Abstract

A new solution for an ultra-low-voltage bulk-driven asynchronous delta sigma modulator (ADSM) is described in the paper. While implemented in a standard 0.18 um CMOS process from TSMC and supplied with VDD = 0.3 V, the circuit offers a 53.3 dB signal to noise and distortion ratio (SNDR), which corresponds to 8.56-bit resolution. Besides, the total power consumption is 37 nW, the signal bandwidth is 62 Hz and the resulting power efficiency is 0.79 pJ/conversion. The above features have been achieved employing a highly linear operational transconductance amplifier (OTA) and a hysteretic comparator based on non-tailed differential pair.

Keywords

Bulk-driven, asynchronous delta-sigma modulator, delta-sigma modulator, low-voltage, low-power, sub 0.5-V circuits.

Authors

KULEJ, T.; KHATEB, F.; FERREIRA, L.

Released

12. 1. 2019

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

Location

USA

ISBN

1063-8210

Periodical

IEEE Trans. on VLSI Systems.

Year of study

27

Number

2, IF: 1.946

State

United States of America

Pages from

316

Pages to

325

Pages count

10

URL

https://doi.org/10.1109/TVLSI.2018.2878625

BibTex

@article{BUT149480,
  author="Tomasz {Kulej} and Fabian {Khateb} and Luis H. C. {Ferreira}",
  title="A 0.3-V 37-nW 53-dB SNDR Asynchronous Delta–Sigma Modulator in 0.18-μm CMOS",
  journal="IEEE Trans. on VLSI Systems.",
  year="2019",
  volume="27",
  number="2, IF: 1.946",
  pages="316--325",
  doi="10.1109/TVLSI.2018.2878625",
  issn="1063-8210",
  url="https://doi.org/10.1109/TVLSI.2018.2878625"
}