Publication detail

All-Pass Time Delay Circuit Magnitude Response Optimization Using Fractional-Order Capacitor

HERENCSÁR, N. KARTCI, A. TLELO-CUAUTLE, E. METIN, B. CICEKOGLU, O.

Original Title

All-Pass Time Delay Circuit Magnitude Response Optimization Using Fractional-Order Capacitor

English Title

All-Pass Time Delay Circuit Magnitude Response Optimization Using Fractional-Order Capacitor

Type

conference paper

Language

en

Original Abstract

Paper presents the integer- and fractional-order cases of a voltage-mode all-pass time delay circuit, or more frequently called as all-pass filter, employing a single negative-type current-controlled current inverting transconductance amplifier and a floating capacitor. Utilization of a fractional-order capacitor (FoC) C0,06 with 12 pF " sec.04 value for magnitude response optimization of the filter is investigated. FoC was emulated via 4th-order Valsa RC network and values optimized using modified least squares quadratic method. In frequency range MHz-I GlIz it shows only +0.5 degree phase angle deviation and the relative pseudo-capacitance error varies from-1.85% to +0.73%. SPICE simulations are given to prove the theory.

English abstract

Paper presents the integer- and fractional-order cases of a voltage-mode all-pass time delay circuit, or more frequently called as all-pass filter, employing a single negative-type current-controlled current inverting transconductance amplifier and a floating capacitor. Utilization of a fractional-order capacitor (FoC) C0,06 with 12 pF " sec.04 value for magnitude response optimization of the filter is investigated. FoC was emulated via 4th-order Valsa RC network and values optimized using modified least squares quadratic method. In frequency range MHz-I GlIz it shows only +0.5 degree phase angle deviation and the relative pseudo-capacitance error varies from-1.85% to +0.73%. SPICE simulations are given to prove the theory.

Keywords

all-pass filter; CCCITA-; fractional-order capacitor; FoC; fractional-order filter; time delay circuit; voltage-mode

Released

05.08.2018

Publisher

IEEE

Location

Windsor, Canada

ISBN

978-1-5386-7392-8

Book

Proceedings of the 2018 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

Pages from

129

Pages to

132

Pages count

4

URL

https://ieeexplore.ieee.org/document/8624059

Full text in the Digital Library

http://hdl.handle.net/11012/194802

Documents

BibTex 


@inproceedings{BUT149105,
  author="Norbert {Herencsár} and Aslihan {Kartci} and Esteban {Tlelo-Cuautle} and Bilgin {Metin} and Oguzhan {Cicekoglu}",
  title="All-Pass Time Delay Circuit Magnitude Response Optimization Using Fractional-Order Capacitor",
  annote="Paper presents the integer- and fractional-order cases of a voltage-mode all-pass time delay circuit, or more frequently called as all-pass filter, employing a single negative-type current-controlled current inverting transconductance amplifier and a floating capacitor. Utilization of a fractional-order capacitor (FoC) C0,06 with 12 pF " sec.04 value for magnitude response optimization of the filter is investigated. FoC was emulated via 4th-order Valsa RC network and values optimized using modified least squares quadratic method. In frequency range MHz-I GlIz it shows only +0.5 degree phase angle deviation and the relative pseudo-capacitance error varies from-1.85% to +0.73%. SPICE simulations are given to prove the theory.",
  address="IEEE",
  booktitle="Proceedings of the 2018 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)",
  chapter="149105",
  doi="10.1109/MWSCAS.2018.8624059",
  howpublished="electronic, physical medium",
  institution="IEEE",
  year="2018",
  month="august",
  pages="129--132",
  publisher="IEEE",
  type="conference paper"
}