Publication detail

Parallelizing boundary surface computation of Chua’s circuit

RÁCZ, Z. GUZAN, M.

Original Title

Parallelizing boundary surface computation of Chua’s circuit

English Title

Parallelizing boundary surface computation of Chua’s circuit

Type

conference paper

Language

en

Original Abstract

This paper introduces a method for performing parallel computations of the boundary surface of Chua's circuit. The presented approach could be characterized as a SIMD method which is based on the utilization of all available CPU cores. Performance comparisons between single and parallelized calculations on different computer systems are included in a table at the end of the article. The best results were observed using the highest compiler optimisation options on 64 bit architecture and using Intel i7 CPUs.

English abstract

This paper introduces a method for performing parallel computations of the boundary surface of Chua's circuit. The presented approach could be characterized as a SIMD method which is based on the utilization of all available CPU cores. Performance comparisons between single and parallelized calculations on different computer systems are included in a table at the end of the article. The best results were observed using the highest compiler optimisation options on 64 bit architecture and using Intel i7 CPUs.

Keywords

cross-section; boundary surface; chaos; Chua’s circuit; attractor; Intel TBB; parallelization; SIMD

Released

19.04.2017

Publisher

UREL FEKT VUT v Brně

Location

Brno

ISBN

978-1-5090-4592-1

Book

Proceedings of 27th International Conference Radioelektronika

Pages from

1

Pages to

4

Pages count

4

BibTex


@inproceedings{BUT143651,
  author="Zsolt {Rácz} and Milan {Guzan}",
  title="Parallelizing boundary surface computation of Chua’s circuit",
  annote="This paper introduces a method for performing parallel computations of the boundary surface of Chua's circuit. The presented approach could be characterized as a SIMD method which is based on the utilization of all available CPU cores. Performance comparisons between single and parallelized calculations on different computer systems are included in a table at the end of the article. The best results were observed using the highest compiler optimisation options on 64 bit architecture and using Intel i7 CPUs.",
  address="UREL FEKT VUT v Brně",
  booktitle="Proceedings of 27th International Conference Radioelektronika",
  chapter="143651",
  doi="10.1109/RADIOELEK.2017.7937582",
  howpublished="online",
  institution="UREL FEKT VUT v Brně",
  year="2017",
  month="april",
  pages="1--4",
  publisher="UREL FEKT VUT v Brně",
  type="conference paper"
}