Publication detail

Testing PCBs Based on Boundary Scan

KOTÁSEK, Z., TUPEC, P., URBIŠ, H.

Original Title

Testing PCBs Based on Boundary Scan

Type

conference paper

Language

English

Original Abstract

The paper describes a practical approach to testing PCBs with Xilinx FPGAs. The approach is based on a PCB netlist analysis, which is revealing the existing connections on the PCB through the Boundary Scan chain and comparing the two results. It is also supposed that the developed software tools will be used for debugging PCBs with Xilinx FPGAs. The goal of the research activities is to develop an easy to use an efficient and user- friendly software tools.

Keywords

Boundary Scan, PCB, FPGA

Authors

KOTÁSEK, Z., TUPEC, P., URBIŠ, H.

RIV year

2003

Released

26. 5. 2003

Publisher

The University of Technology Košice

Location

Košice

ISBN

80-7099-509-2

Book

Proceedings of International Carpathian Control Conference

Pages from

119

Pages to

122

Pages count

4

BibTex

@inproceedings{BUT14165,
  author="Zdeněk {Kotásek} and Pavel {Tupec} and Hynek {Urbiš}",
  title="Testing PCBs Based on Boundary Scan",
  booktitle="Proceedings of International Carpathian Control Conference",
  year="2003",
  pages="119--122",
  publisher="The University of Technology Košice",
  address="Košice",
  isbn="80-7099-509-2"
}