Publication detail

Fractional-Order Oscillator Design Using Unity-Gain Voltage Buffers and OTAs

KARTCI, A. HERENCSÁR, N. KOTON, J. BRANČÍK, L. VRBA, K. TSIRIMOKOU, G. PSYCHALINOS, C.

Original Title

Fractional-Order Oscillator Design Using Unity-Gain Voltage Buffers and OTAs

English Title

Fractional-Order Oscillator Design Using Unity-Gain Voltage Buffers and OTAs

Type

conference paper

Language

en

Original Abstract

In this study, a new voltage-mode fractional-order oscillator using two unity-gain voltage buffers, two operational transconductance amplifiers, one resistor, and two capacitors is presented. The design procedure of integer-order as well as fractional-order oscillator employing in total 20 MOS transistors is discussed. Effects of fractional-order capacitors on amplitude, phase, condition of oscillation, and frequency of oscillation are shown. Various case examples are given while SPICE simulations using TSMC 0.35 µm level-3 CMOS process parameters with ±1.65 V supply voltages verify their operation and compare with theoretical ones.

English abstract

In this study, a new voltage-mode fractional-order oscillator using two unity-gain voltage buffers, two operational transconductance amplifiers, one resistor, and two capacitors is presented. The design procedure of integer-order as well as fractional-order oscillator employing in total 20 MOS transistors is discussed. Effects of fractional-order capacitors on amplitude, phase, condition of oscillation, and frequency of oscillation are shown. Various case examples are given while SPICE simulations using TSMC 0.35 µm level-3 CMOS process parameters with ±1.65 V supply voltages verify their operation and compare with theoretical ones.

Keywords

fractional-order circuit; fractional-order oscillator; flipped voltage follower; FVF; operational transconductance amplifier; OTA; voltage buffer; voltage-mode

Released

06.08.2017

Publisher

IEEE

Location

Boston, USA

ISBN

978-1-5090-6389-5

Book

Proceedings of the 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)

Pages from

555

Pages to

558

Pages count

4

URL

http://ieeexplore.ieee.org/document/8052983/

Full text in the Digital Library

http://hdl.handle.net/11012/70108

Documents

BibTex 


@inproceedings{BUT138292,
  author="Aslihan {Kartci} and Norbert {Herencsár} and Jaroslav {Koton} and Lubomír {Brančík} and Kamil {Vrba} and Georgia {Tsirimokou} and Costas {Psychalinos}",
  title="Fractional-Order Oscillator Design Using Unity-Gain Voltage Buffers and OTAs",
  annote="In this study, a new voltage-mode fractional-order oscillator using two unity-gain voltage buffers, two operational transconductance amplifiers, one resistor, and two capacitors is presented. The design procedure of integer-order as well as fractional-order oscillator employing in total 20 MOS transistors is discussed. Effects of fractional-order capacitors on amplitude, phase, condition of oscillation, and frequency of oscillation are shown. Various case examples are given while SPICE simulations using TSMC 0.35 µm level-3 CMOS process parameters with ±1.65 V supply voltages verify their operation and compare with theoretical ones.",
  address="IEEE",
  booktitle="Proceedings of the 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)",
  chapter="138292",
  doi="10.1109/MWSCAS.2017.8052983",
  howpublished="online",
  institution="IEEE",
  year="2017",
  month="august",
  pages="555--558",
  publisher="IEEE",
  type="conference paper"
}