Publication detail

Packet Generators on Field Programmable Gate Array Platform

SMÉKAL, D. HAJNÝ, J. MARTINÁSEK, Z.

Original Title

Packet Generators on Field Programmable Gate Array Platform

English Title

Packet Generators on Field Programmable Gate Array Platform

Type

conference paper

Language

en

Original Abstract

With the growing speed of computer networks, we need to test our solutions, network conditions, and topologies using high-speed traffic generators. The main contribution of this paper is 1) the theoretical proposal of a pseudo-random number generator (PRNG) algorithm that is usable for hardware-accelerated IP traffic generators and 2) the practical proposal of a novel design and implementation of an FPGA-based traffic generator that provides the high-speed generation of IP traffic for testing purposed, in particular for the Denial-of-Service (DoS) security testing. We present a solution for network cards based on FPGA and the NetCOPE development platform, in particular the NFB-40G2 cards. Using this platform, we explain the process of creating an IP packet and propose the VHDL architecture of the packet generator.

English abstract

With the growing speed of computer networks, we need to test our solutions, network conditions, and topologies using high-speed traffic generators. The main contribution of this paper is 1) the theoretical proposal of a pseudo-random number generator (PRNG) algorithm that is usable for hardware-accelerated IP traffic generators and 2) the practical proposal of a novel design and implementation of an FPGA-based traffic generator that provides the high-speed generation of IP traffic for testing purposed, in particular for the Denial-of-Service (DoS) security testing. We present a solution for network cards based on FPGA and the NetCOPE development platform, in particular the NFB-40G2 cards. Using this platform, we explain the process of creating an IP packet and propose the VHDL architecture of the packet generator.

Keywords

Packet; Generator; FPGA; LFSR; pseudo-random number; NetCOPE

Released

05.07.2017

Location

Barcelona, Španělsko

ISBN

978-1-5090-3982-1

Book

2017 40th International Conference on Telecommunications and Signal Processing (TSP)

Pages from

97

Pages to

100

Pages count

4

URL

Documents

BibTex


@inproceedings{BUT135463,
  author="David {Smékal} and Jan {Hajný} and Zdeněk {Martinásek}",
  title="Packet Generators on Field Programmable Gate Array Platform",
  annote="With the growing speed of computer networks, we need to test our solutions, network conditions, and topologies using high-speed traffic generators. The main contribution of this paper is 1) the theoretical proposal of a pseudo-random number generator (PRNG) algorithm that is usable for hardware-accelerated IP traffic generators and 2) the practical proposal of a novel design and implementation of an FPGA-based traffic generator that provides the high-speed generation of IP traffic for testing purposed, in particular for the Denial-of-Service (DoS) security testing. We present a solution for network cards based on FPGA and the NetCOPE development platform, in particular the NFB-40G2 cards. Using this platform, we explain the process of creating an IP packet and propose the VHDL architecture of the packet generator.",
  booktitle="2017 40th International Conference on Telecommunications and Signal Processing (TSP)",
  chapter="135463",
  doi="10.1109/TSP.2017.8075944",
  howpublished="online",
  year="2017",
  month="july",
  pages="97--100",
  type="conference paper"
}