Publication detail

On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems

STRNADEL, J.

Original Title

On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

The paper details design of a hardware unit for preventing real-time systems from overloads caused by excessive interrupt rates. Novelty of the hardware can be seen in the fact it is able to adapt interrupt service rate to the RT system load and to the actual priority assignment policy. The load is monitored on basis of special low-overhead signals produced by the system for this purpose. The hardware is designed to preprocess all interrupts before they arrive to the system. The hardware is ready to buffer each interrupt-related communication until the system is underloaded or running an activity having a lower priority comparing to the interrupt. Design of the hardware was described in VHDL and synthesized into Xilinx Spartan-6 devices. Details such as buiding blocks, overheads and limits related to the realization are presented in this paper.

Keywords

task, operating system, load monitoring, interrupt control, scheduling, overload prevention, priority space

Authors

STRNADEL, J.

RIV year

2013

Released

8. 4. 2013

Publisher

IEEE Computer Society

Location

Brno

ISBN

978-1-4673-6133-0

Book

Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems

Pages from

24

Pages to

29

Pages count

6

URL

https://www.fit.vut.cz/research/publication/10235/

BibTex

@inproceedings{BUT103418,
  author="Josef {Strnadel}",
  title="On Design of Priority-Driven Load-Adaptive Monitoring-Based Hardware for Managing Interrupts in Embedded Event-Triggered Real-Time Systems",
  booktitle="Proceedings of the IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems",
  year="2013",
  pages="24--29",
  publisher="IEEE Computer Society",
  address="Brno",
  doi="10.1109/DDECS.2013.6549783",
  isbn="978-1-4673-6133-0",
  url="https://www.fit.vut.cz/research/publication/10235/"
}