Project detail

Formální postupy v diagnostice číslicových obvodů - verifikace testovatelného návrhu

Duration: 01.01.2001 — 31.12.2003

On the project

Narůstající složitost číslicových obvodů klade stále vyšší nároky na jejich testování. Uplatnění diagnostických principů se stalo nedílnou součástí syntézy číslicových obvodů. Současně s probíhající syntézou obvodu jsou tedy zvažovány možnosti jeho testování - např. pomocí metody úplný scan, částečný scan nebo autonomního testování (BIST). Posuzují se různé aspekty návrhu obvodu - z hlediska diagnostiky je důležitou vlastností řiditelnost/pozorovatelnost vstupů/výstupů prvků navrhovaného obvodu.Doposud publikované diagnostické metodiky uplatňované při syntéze obvodu jsou založeny na heuristických postupech, při nichž je analyzována struktura obvodu. Tyto heuristické postupy jsou různé pro různé typy obvodů. Cílem tohoto projektu je vytvoření formálního aparátu použitelného pro reprezentaci diagnostických vlastností jednotlivých prvků a obvodu jako celku a založeného na pojmech teorie množin, teorie grafů a matematické logiky. Použitelnost tohoto aparátu bude ověřena při tvorbě algoritmů využitelných při syntéze číslicového obvodu. Účinnost těchto postupů bude v průběhu řešení ověřována na testovacích obvodech (benchmark) a na obvodech vyvíjených pro praktické aplikace. Zároveň s tímto nosným tématem bude věnována pozornost metodám analytickým. Výsledky obou principů budou průběžně srovnávány. Bude rovněž posouzena možnost kombinace obou typů metodik.

Description in English
The growing complexity of integrated circuits confronts the manufacturers with the problem of testability. The implementation of diagnostic principles has become an integral part of the process of digital circuit synthesis. During the synthesis the topics of testability are evaluated simultaneously with the synthesis - e. g. full scan, partial scan or BIST methods. Different aspects of the circuit design are evaluated and the controllability/observability of the inputs/outputs of internal elements of the unit under design is an important feature. The diagnostic methodologies utilized during the circuit synthesis are based on heuristic approaches during which the structure of the circuit is analysed. These heuristic approaches are different for different types of circuits.The goal of this project is the development of formal tools which can be used to represent diagnostic features of a circuit and its internal elements, based on theory of sets, theory of graphs and mathematical logic concepts. The applicability of the formal tools will be verified on benchmark circuits and on circuits developed for practical applications. Together with this main theme the research into analytical approaches will be made. The results gained for both approaches will be currently compared. The possibility of combining both approaches will also be verified.

Mark

GA102/01/1531

Default language

Czech

People responsible

Kotásek Zdeněk, doc. Ing., CSc.
- principal person responsible (1980-01-01 - not assigned)
Drábek Vladimír, doc. Ing., CSc.
- fellow researcher (2001-01-01 - 2003-12-31)
Růžička Richard, doc. Ing., Ph.D., MBA
- fellow researcher (2001-01-01 - 2003-12-31)
Sekanina Lukáš, prof. Ing., Ph.D.
- fellow researcher (2001-01-01 - 2003-12-31)
Strnadel Josef, Ing., Ph.D.
- fellow researcher (2001-01-01 - 2003-12-31)
Zbořil František, doc. Ing., CSc.
- fellow researcher (2001-01-01 - 2003-12-31)

Units

Faculty of Information Technology
- (2001-01-01 - not assigned)

Funding resources

Czech Science Foundation - Standardní projekty
- whole funder

Results

MUSIL, V. The n-bit generic model of LFSR. In Electronic Devices and Systems EDS 01. Noise and Non-Linearity Testing of Modern Electronics Components - Workshop. Proceedings. Brno: Ing. Zdeněk Novotný, CSc., 2001. p. 165 ( p.)ISBN: 80-214-1960-1.
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STRNADEL, J. Analýza a zlepšení testovatelnosti číslicového obvodu na úrovni meziregistrových přenosů. Brno: 2004.
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STRNADEL, J., KOTÁSEK, Z., RŮŽIČKA, R. Formal and Analytical Approaches to the Testability Analysis - the Comparison. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2001. Gyor: SZIF-UNIVERSITAS Ltd., Hungary, 2001. p. 123-128. ISBN: 963-7175-16-4.
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KOTÁSEK, Z., STRNADEL, J., RŮŽIČKA, R., ZBOŘIL, F. Two Level Testability System. In Proceedings of the 35th Spring International Conference MOSIS'01. Ostrava: 2001. p. 433-440. ISBN: 80-85988-57-7.
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HLAVIČKA, J., KOTÁSEK, Z., STRNADEL, J., RŮŽIČKA, R. Interactive Tool for Behavioral Level Testability Analysis. In Proceedings of the IEEE ETW 2001. Stockholm: 2001. p. 117-119.
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STRNADEL, J., KOTÁSEK, Z. RTL Testability Analysis Based on Genetic Algorithm Implementation. In Proceedings of the Tenth ICNACSA. Plovdiv: unspecified agency, 2001. p. 89 ( p.)
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STRNADEL, J., KOTÁSEK, Z. RTL Testability Analysis Based on Genetic Algorithm Implementation. In Proceedings of the IWCIT'01. Ostrava: Faculty of Electrical Engineering and Computer Science, VSB-TU Ostrava, 2001. p. 83-88. ISBN: 80-7078-907-7.
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DRÁBEK, V. Configurable Computing. In Advanced Simulation of Systems. Ostrava: 2001. p. 59-63. ISBN: 80-85988-61-5.
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KOTÁSEK, Z., STRNADEL, J. Analytic Approach to RTL Testability Analysis. In Proceedings of 7th Conference Student FEI 2001. Brno: Brno University of Technology, 2001. p. 363 ( p.)ISBN: 80-214-1860-5.
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SEKANINA, L., DRÁBEK, V. Automatic Design of Image Operators Using Evolvable Hardware. In Proc. of 5th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Brno: Brno University of Technology, 2002. p. 132-139. ISBN: 80-214-2094-4.
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SLLAME M., A., DRÁBEK, V. A Design Space Exploration Scheme for High-Level Synthesis Systems. In Proceedings of 36th International Conference MOSIS '02 Modelling and Simulation of Systems. Vol. I. Ostrava: 2002. p. 305-312. ISBN: 80-85988-71-2.
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SEKANINA, L. Automata of Evolvable Computational Machines. In Proc. ot 8th conference Student EEICT. Brno: Brno University of Technology, 2002. p. 491-495. ISBN: 80-214-2116-9.
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STRNADEL, J. Evaluating Cost/Quality Trade-off Solutions Proposed During a DFT Process. In Proceeding of 8th Conference Student EEICT 2002. Brno: Brno University of Technology, 2002. p. 506-510. ISBN: 80-214-2116-9.
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RŮŽIČKA, R. The Formal Approach to the RTL Test Application Problem Using Petri Nets. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems 2002. Brno: Faculty of Information Technology BUT, 2002. p. 78-86. ISBN: 80-214-2094-4.
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SEKANINA, L. Evolution of digital circuits operating as image filters in dynamically changing environment. In Mendel 2002 - 8th International Conference on Soft Computing. Brno: Brno University of Technology, 2002. p. 33-38. ISBN: 80-214-2135-5.
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SLLAME M., A., SEKANINA, L. An Evolutionary-Based Algorithm to the Module Selection Process in High-Level Synthesis. In Mendel 2002 - 8th International Conference on Soft Computing. Brno: Brno University of Technology, 2002. p. 87-92. ISBN: 80-214-2135-5.
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SEKANINA, L. Evolvable Computational Machines: Formal Approach. In Intelligent Technologies - Theory and Applications, E-ISCI 2002. Frontiers in Artificial Intelligence and Applications. Amsterdam: IOS Press, 2002. p. 166-172. ISBN: 1-58603-256-9.
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SLLAME M., A., DRÁBEK, V. An Efficient List-Based Scheduling Algorithm for High-Level-Synthesis. In EUROMICRO Symposium on Digital System Design (DSD2002): Architecture, Methods and Tools, IEEE Computer Society. IEEE Computer Society. Dortmund, Germany: IEEE Computer Society Press, 2002. p. 316-323. ISBN: 0-7695-1790-0.
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SLLAME M., A. Efficient Design Space Characterization Toward Realizing High-Performance Digital systems. In Proceedings of Electronic Devices and Systems EDS'02 Conference. Proceedings. Brno: Brno University of Technology, 2002. p. 144-149. ISBN: 80-214-2180-0.
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SLLAME M., A., SEKANINA, L. An Evolutionary-Based Algorithm to the Module Selection Problem with Resource Sharing in High-Level Synthesis (Extended Abstract). In Advances in Nature-Inspired Computation: The PPSN VII Workshops. Reading: PEDAL, Department of Computer Science, University of Reading, 2002. p. 45-46. ISBN: 0-9543481-0-9.
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STRNADEL, J., KOTÁSEK, Z. Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. In Proceedings of Euromicro Symposium on Digital System Design Architectures, Methods and Tools DSD'2002. Los Alamitos: IEEE Computer Society Press, 2002. p. 166-173. ISBN: 0-7695-1790-0.
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SEKANINA, L., DRÁBEK, V. A Survey of Bioinspired Methods for Design of Fault Tolerant Reconfigurable Architectures. In Proc. of the 8th Biennial Baltic Electronics Conference. Tallinn: Talinn Technical University, 2002. p. 355-358. ISBN: 9985-59-292-1.
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ZBOŘIL, F., KOTÁSEK, Z., MIKA, D., STRNADEL, J. The Identification of Feedback Loops in RTL Structures. In Proceedings of The fifth International Scientific Conference Electronic Computers and Informatics 2002. Edition 55. Košice: The University of Technology Košice, 2002. p. 142-147. ISBN: 80-7099-879-2.
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MIKA, D., KOTÁSEK, Z., STRNADEL, J. Test Controller Design Based on VHDL Source File Analysis. In Proceedings of The Fifth International Scientific Conference Electronic Computers and Informatics 2002. VIENALA Press, Edition: 55. Letná 42, 040 01 TU Košice: The University of Technology Košice, 2002. p. 135-141. ISBN: 80-7099-879-2.
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DRÁBEK, V., SEKANINA, L. Basic Principles of Bio-Inspired Approaches to Fault Tolerance: Tutorial. In Design for Test of Systems on Chip: Digital Test. Tallinn: Talinn Technical University, 2002. p. 1-48. ISBN: 0000-00-000-0.
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RŮŽIČKA, R. VHDL Circuit Description Transparency Analysis. In Proceedings of the Fifth International Scientific Conference Electronic Computers and Informatics 2002. Košice: Faculty of Electrical Engineering and Informatics, University of Technology Košice, 2002. p. 194-199. ISBN: 80-7099-879-2.
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SEKANINA, L. Nanostructures and bio-inspired computer engineering (Abstract). In Nano'02 (Abstracts). Brno: Akademické nakladatelství CERM, 2002. p. 74-74. ISBN: 80-7204-258-0.
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SEKANINA, L. Nanostructures and bio-inspired computer engineering. In Proceedings of Nano02. Ostrava: Repronis, 2002. p. 233-236. ISBN: 80-7329-027-8.
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MIKA, D. Uplatnění formálních postupů při návrhu řadiče testu číslicového systému. In Počítačové Architektury & Diagnostika Pracovní seminář pro studenty doktorského studia Sborník příspěvků. Brno: Fakulta informačních technologií VUT v Brně, 2003. s. 17-23. ISBN: 80-214-2471-0.
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STRNADEL, J. Analýza a zlepšení testovatelnosti RTL číslicového obvodu. In Sborník příspěvků ze semináře Počítačové Architektury & Diagnostika. Brno: Fakulta informačních technologií VUT v Brně, 2003. s. 24-29. ISBN: 80-214-2471-0.
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SLLAME M., A. A Pipeline Scheduling Algorithm for High-Level Synthesis. In Proc. of IFAC Workshop on Programmable Devices and Systems Conference. Ostrava: Elsevier Science, 2003. p. 178-183. ISBN: 0-08-044130-0.
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MIKA, D., KOTÁSEK, Z. Proc. of IFAC Workshop on Programmable Devices and Systems Conference. In Proc. of IFAC Workshop on Programmable Devices and Systems Conference. Ostrava: Faculty of Electrical Engineering and Computer Science, VSB-TU Ostrava, 2003. p. 447-452. ISBN: 0-08-044130-0.
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STRNADEL, J. Nested Loops Degree Impact on RTL Digital Circuit Testability. In Programmable Devices and Systems. Oxford: Elsevier Science, 2003. p. 202-207. ISBN: 0-08-044130-0.
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KOTÁSEK, Z., MIKA, D., STRNADEL, J. Proceeding of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. In Proceeding of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. Poznaň: Publishing House of Poznan University of Technology, 2003. p. 233-238. ISBN: 83-7143-557-6.
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STRNADEL, J. Algebraic Analysis of Feedback Loop Dependencies in Order of Improving RTL Digital Circuit Testability. In Proceedings of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems. Poznan: Publishing House of Poznan University of Technology, 2003. p. 303-304. ISBN: 83-7143-557-6.
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SEKANINA, L., RŮŽIČKA, R. On the Automatic Design of Testable Circuits. In Proceedings of IEEE Workshop on Design nad Diagnostics of Electronic Circuits and Systems. Poznań: Publishing House of Poznan University of Technology, 2003. p. 299-300. ISBN: 83-7143-557-6.
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STRNADEL, J. Scan Layout Encoding by Means of a Binary String. In Proceedings of 37th International Conference on Modelling and Simulation of Systems. Ostrava: 2003. p. 115-122. ISBN: 80-85988-86-0.
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SEKANINA, L., RŮŽIČKA, R. Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers. In The 2003 NASA/DoD Conference on Evolvable Hardware. Los Alamitos: IEEE Computer Society Press, 2003. p. 135-144. ISBN: 0-7695-1977-6.
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RŮŽIČKA, R., ZBOŘIL, F. Representation of Datapath Structure in Predicate Logic and its Implementation in Prolog. In Proceedings of International Carpathian Control Conference. Košice: The University of Technology Košice, 2003. p. 727-730. ISBN: 80-7099-509-2.
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KOTÁSEK, Z., TUPEC, P., URBIŠ, H. Testing PCBs Based on Boundary Scan. In Proceedings of International Carpathian Control Conference. Košice: The University of Technology Košice, 2003. p. 119-122. ISBN: 80-7099-509-2.
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KOTÁSEK, Z., URBIŠ, H. USB-to-IDE Adapter Design and Implementation. In 6th International Workshopn on Electronics, Control, Measurment and Signals. Liberec: Liberec University of Technology, 2003. p. 315-319. ISBN: 80-7083-708-X.
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KOTÁSEK, Z., MIKA, D., STRNADEL, J. Test scheduling for embedded systems. In Proceedings EUROMICRO Symposium on Digital System Design - Architectures, Methods and Tools DSD 2003. Belek: IEEE Computer Society Press, 2003. p. 463-467. ISBN: 0-7695-2003-0.
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RŮŽIČKA, R. Testable Design Verification Using Petri Nets. In Proceedings of Euromicro Symposium on Digital System Design 2003. Los Alamitos, CA: IEEE Computer Society Press, 2003. p. 304-311. ISBN: 0-7695-2003-0.
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MUSIL, V., VLČEK, K., MITRYCH, J., KOVALSKÝ, J. Návrh obvodů v jazycích VHDL a Verilog. Sdělovací technika, 2001, roč. 2001, č. 11,12, s. 16 ( s.)ISSN: 0036-9942.
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SEKANINA, L. Image Filter Design with Evolvable Hardware. Lecture Notes in Computer Science, 2002, vol. 2002, no. 2279, p. 255-266. ISSN: 0302-9743.
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SEKANINA, L., DRÁBEK, V. Soft-hardware. Vesmír, 2002, roč. 81, č. 7, s. 393-395. ISSN: 0042-4544.
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SEKANINA, L. Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware. Lecture Notes in Computer Science, 2003, vol. 2003, no. 2606, p. 186-197. ISSN: 0302-9743.
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SEKANINA, L. From Implementations to a General Concept of Evolvable Machines. Lecture Notes in Computer Science, 2003, vol. 2003, no. 2610, p. 424-433. ISSN: 0302-9743.
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SEKANINA, L. Evolvable Components - From Theory to Hardware Implementations. Natural Computing Series. Natural Computing Series. Berlin: Springer Verlag, 2003. 194 p. ISBN: 3-540-40377-9.
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HLAVIČKA, J., MARINISSEN, E., NOVÁK, O., STRAUBE, B., KOTÁSEK, Z., RŮŽIČKA, R. Proceedings of 5th International Workshop IEEE Design and Diagnostics of Electronic Circuits and Systems. Brno: Faculty of Information Technology BUT, 2002. p. 0 ( p.)ISBN: 80-214-2094-4.
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DRÁBEK, V. Montgomery Multiplication in GF(p) and GF(2^n). Brno: Brno University of Technology, 2003. p. 106-109. ISBN: 80-214-2452-4.
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KOTÁSEK, Z., SEKANINA, L., RŮŽIČKA, R. Sborník pracovního semináře "Počítačové architektury a diagnostika" pro studenty doktorského studia. Brno: Ústav počítačových systémů FIT VUT v Brně, 2003. s. 0 ( s.)ISBN: 80-214-2471-0.
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RŮŽIČKA, R. Formální přístup k analýze testovatelnosti číslicových obvodů na úrovni RT. Brno: 2002. s. 0 ( s.)
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SEKANINA, L. Component Approach to Evolvable Systems. Brno: 2002. p. 0 ( p.)
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SLLAME M., A., DRÁBEK, V. Specification and Synthesis of Reusable Modules in VHDL. In Proceedings of fourth International Wokshop on IEEE Design and Diagnostics of Electronic Circuits and Systems IEEE DDCSE01. Gyor, Hungary: SZIF-UNIVERSITAS Ltd., Hungary, 2001. p. 137-140. ISBN: 963-7175-16-4.
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