Branch Details
Computer Science and Engineering
Original title in Czech: Výpočetní technika a informatikaFITAbbreviation: DVI4Acad. year: 2015/2016
Programme: Computer Science and Engineering
Length of Study:
Profile
The goal of the doctoral study programme is to provide outstanding graduates from the MSc study programme with a specialised university education of the highest level in certain fields of information technology, including especially the areas of information systems, computer-based systems and computer networks, computer graphics and multimedia, and intelligent systems. The education obtained within this study programme also comprises a training and attestation for scientific work.
Key learning outcomes
- Graduates from the doctoral study programme are trained to independently work in research, development, or management.
- They are able to solve and/or to lead teams solving advanced conceptual, research, development, or production problems in the area of contemporary information technology and its applications.
- They can be engaged to work on creative tasks, to lead research and development teams, or to work in management of companies or organizations whenever there are required abilities to work in an independent and creative way, to analyze complex problems, and to propose and realize new and original solutions. Graduates from the doctoral study programme can also teach and/or scientifically work at universities.
Guarantor
Issued topics of Doctoral Study Program
- Accelerated Algorothms of Signal and Image Processing
- Accelerated Algorothms of Signal and Image Processing
- Accelerated Algorothms of Signal and Image Processing
- Advanced Algorithms of Video Processing
The topic focuses algorithms of video processing. Its main goal is to research algorithms so that their features and application possibilities are better understood, so that they are deeply analyzed, so that they are improved or newly created, and so that they are efficiently implemented e.g. in CPU, in CPU with acceleration through SSE instructions, in embeded systems, in embedded systems with FPGA, or in other systems. The programming work is expected in C, C++, C#, assembly language, CUDA, OpenCl, or VHDL. The algorithms of interest include:
- recognition of scene contents, events, and general semantics of video sequences,
- classification of video sequences through deep convolution networks neural networks, space-time features, etc.,
- object tracking in video using modern methods (such as TLD or particle tracking)
- assessment of video content similarities and its contents e.g. through mutual information, semantics analysis,
- new algorithms of video Processing suitable e.g. for mobile technology and/or embedded systems,
- algorithms of video compression and analysis through frequency or wavelet transforms or similar methods...
After mutual agreement, individually selected algorithms can be considered as well as soon as they do belong to the general topic.
- Advanced methods for monitoring and analysis of mobil communication
- Advanced Methods of Computational Photography
The project is concerned with advanced methods of computational photography. The aim is to research new computational photography methods, which comprises software solutions potentially supported by new optics and/or hardware. Our interest is on HDR image and video processing, color-to-grayscale conversions, spectral imaging, and others.
- Further information: http://cadik.posvete.cz/tmo/
- Contact: http://cadik.posvete.cz/
- Cooperation and research visits with leading research labs are possible (MPII Saarbrücken, Germany, Disney Research Zurich, Switzerland, INRIA Bordeaux, France)
- Advanced methods of practicel reasoning in the BDI systems.
- Advanced methods of querying image and video data
- Advanced Methods of Real-Time Rendering
- Analysis of Anonymisation Networks Security
Tutor: Hanáček Petr, doc. Dr. Ing.
- Analysis of Attacks on Wireless Networks
Tutor: Hanáček Petr, doc. Dr. Ing.
- Analysis of moving objects
- Augmented Reality on Mobile Devices
The goal of the work is to research and create algorithms that will allow for running augmented reality on mobile (ultramobile) devices. It mainly concerns algorithms of pose estimation in the space by the means of computer vision and by using sensors embedded in the device. Furthermore, the work will elaborate on algorithms of rendering of virtual elements into the real-world scene and on applications of augmented reality on mobile devices.
- Automated Intelligent Testing, Analysis, and Software Quality Assurance
- Automatic workload balancing on heterogeneous architectures
- Autonomous Inelligent Systems Driven by a Model
- Bayseian networks - constructions and applications
- Communication Infrastructure for Intelligent Buildings or Vehicles
Tutor: Hanáček Petr, doc. Dr. Ing.
- Concept of algorithms for removal of influence of skin diseases on the process for fingerprint recognition
- Cooperation among robots
- Dependability Issues of Operating Systems and Applications They Control
Modern operating systems (OS) must meet many requirements not only in terms of flexibility and efficiency of their execution on recent computing platforms, but also in terms of dependability of their kernels and services they provide to the application layer. The aim of the project is:
- to analyze the actual state in the area of dependability of OS kernels / services,
- to identify (in terms of dependability) negative effects and their impact to dependability of the application layer,
- to propose a method for increasing dependability of OS kernels / services,
- to evaluate an impact of the method to dependability of OS kernels / services and operation of the application layer.
The project can be oriented into various directions, such as low-power applications / OS or application / OS designed to run in an embedded or a multi-core environment. During the project, a "conventional" OS such as Unix, Linux, Android, Windows, iOS or a specialized OS such as QNX, uC/OS-I (II, III), FreeRTOS, MQX can be utilized.
Tutor: Strnadel Josef, Ing., Ph.D.
- Detection and localization of (living) people behind obstacles
- Detection and Re-Identification of Objects in Image and Video
- Omnidirectional object detection in real time
- Re-identification of detected objects, e.g. in shots from different cameras or at different points in time
- Focused on statinary surveillance cameras
- Focused on automatic traffic surveillance
- Detection and Re-Identification of Objects in Image and Video
- Omnidirectional object detection in real time
- Re-identification of detected objects, e.g. in shots from different cameras or at different points in time
- Focused on statinary surveillance cameras
- Focused on automatic traffic surveillance
- Detection and Re-Identification of Objects in Image and Video
- Omnidirectional object detection in real time
- Re-identification of detected objects, e.g. in shots from different cameras or at different points in time
- Focused on statinary surveillance cameras
- Focused on automatic traffic surveillance
- Detection and Re-Identification of Objects in Image and Video
- Omnidirectional object detection in real time
- Re-identification of detected objects, e.g. in shots from different cameras or at different points in time
- Focused on statinary surveillance cameras
- Focused on automatic traffic surveillance
- Detection and Re-Identification of Objects in Image and Video
- Omnidirectional object detection in real time
- Re-identification of detected objects, e.g. in shots from different cameras or at different points in time
- Focused on statinary surveillance cameras
- Focused on automatic traffic surveillance
- Efficient Methods for Capturing and Preservation Network Forensic Data
- Energy Reducing Compiler Optimization
As you probably know, a compiler comprises from a language depending analytic part (front-end) which is producing a revised internal representation and a following part (back-end) which is generating a result object code or an assembler code.
The methodology for the front-end is already solved from the practical point of view many years and it is thought on a bachelor level of study. There are some generators of the analytical compiler part which are mainly based on the LALR grammars. These ones are able to generate the analytical part and a context depending part is easy built according to a known methodology. For some branches we use moreover the C/C++ language only. The front-end of such compiler is freely down able on the net. When we sufficiently design the internal representation, the front-end generator is depending on the input language only. Such internal representations are existing. The definition language pro the generator is mainly an attribute grammar.
Real practical problems occur in the back-end generation. An amount of processor architectures is high and moreover is permanently increasing in connection with mobile phones, and other embedded systems, Internet of Things, medical devices, automotive devices etc. One of the main reasons is a collision of using of available processors with already developed compilers and simultaneously large power consumption. These designed devices cannot use such processors by reasons of power consumption and often also of a license price. So, the number and variety of the processor architecture is quickly increasing. It will be sufficient to keep at disposition for the back-end a similar generating tool like for the front-end. In such way, we can to a great extend to speed-up a transport of applications (written mainly in the C language) on the new processors.
For the sake of increasing of complexity of embedded systems and non-linear microprocessor architectures, we need high optimized compilers for decreasing of the complexity of such platforms and their power dissipation. An power consumption of actual microprocessors is solved by using of a dynamical power consumption which can be rapidly decreased by an elimination of memory approaches, minimization of performed cycles, and minimization of the triggering activities on buses.
What we can link to?
In a frame of the Lissom group research, a reconfigurable C compiler grew. It is now a part of the Codasip Studio of the Codasip Ltd. (www.codasip.com) and also for our university.
The aim of this work is a critical evaluation of the present state of the research and methods and a design of an effective generation methodology and the generator with a focus to an effective power consumption. This work will solved optimization by a register assignment for non-regular architectures, and e.g. an after pass code optimizations for a minimization of the dynamic triggering on instruction memory busses. More information verbally.
Possible engagement in paid activities:
-basic stipendium of the PhD. program
-an remuneration from grant projects
-some part time job in the co-operating company
-possible to pass an internship program
Contact and information
Prof. Ing. Tomáš Hruška, CSc. - hruska@fit.vutbr.cz - Environment for Modeling and Optimization Software Engineering Processes
- Evolutionary algorithms for approximate computing
- Evolutionary algorithms for approximate computing
- Evolutionary algorithms for approximate computing
- Fault tolerant systems design automation
- Formal methods in evolutionary design and optimization of digital circuits
- Formal Models of Distributed Computation
- Formal Verification of Concurrent Programs with an Unbounded of Concurrent Threads
- General Purpose GPU
- Generating phase of the Reconfigurable Compiler
As you probably know, a compiler comprises from a language depending analytic part (front-end) which is producing a revised internal representation and a following part (back-end) which is generating a result object code or an assembler code.
The methodology for the front-end is already solved from the practical point of view many years and it is thought on a bachelor level of study. There are some generators of the analytical compiler part which are mainly based on the LALR grammars. These ones are able to generate the analytical part and a context depending part is easy built according to a known methodology. For some branches we use moreover the C/C++ language only. The front-end of such compiler is freely down able on the net. When we sufficiently design the internal representation, the front-end generator is depending on the input language only. Such internal representations are existing. The definition language pro the generator is mainly an attribute grammar.
Real practical problems occur in the back-end generation. An amount of processor architectures is high and moreover is permanently increasing in connection with mobile phones, and other embedded systems, Internet of Things, medical devices, automotive devices etc. One of the main reasons is a collision of using of available processors with already developed compilers and simultaneously large energy consumption. These designed devices cannot use such processors by reasons of energy consumption and often also of a license price. So, the number and variety of the processor architecture is quickly increasing. It will be sufficient to keep at disposition for the back-end a similar generating tool like for the front-end. In such way, we can to a great extend to speed-up a transport of applications (written mainly in the C language) on the new processors. The back-end generating is a relatively new topic which is not taught in the university curricula (at FIT as well).What we should possess:
-an internal representation as a input of the transformation,
-the language for the processor definition as the generator input,
-a suitable retargetable back-end
So, we want to generate a quick and effective compiler (currently for the C language only) for different processor architectures which will be described by the definition language.
What we can link to?
The aim of this work is a critical evaluation of the present state of the research and methods and a design of an effective generation methodology and the generator as well. The design of a transportable reconfigurable C/C++ compiler for the VLIW processor architectures.
In a frame of the Lissom group research, a reconfigurable C compiler grew. It is now a part of the Codasip Studio of the Codasip Ltd. (www.codasip.com) and also for our university. We have some experience with this research. It is sure, that we do a research on the world level which is practically requested and which is not definitely solved. There are definition languages, the internal representation, and the reconfigurable C compiler. We have developed a workable generator, but it is not sure, whether it is sufficiently effective for sufficient scale of architectures.More information verbally.
Possible engagement in paid activities:
-a basic stipendium of the PhD. program
-an remuneration from grant projects
-some part time job in the co-operating company
-possible to pass an internship program
Contact and information Prof. Ing. Tomáš Hruška, CSc. - hruska@fit.vutbr.cz - Hardware Acceleration of Application Protocols
- Hardware Acceleration of Application Protocols
- Hardware Acceleration of Application Protocols
- High Performance computing on multi-GPU clusters
- Image and video quality assessment metrics
The project deals with image and video quality assessment metrics (IQM). The aim is to explore new ways how to incorporate human visual system properties into IQM. In particular, we will consider perception of HDR images, and utilization of additional knowledge (in form of metadata, 3D information, etc.) about the tested scenes.
- Further information: http://cadik.posvete.cz/iqm/
- Contact: http://cadik.posvete.cz/
- Cooperation and research visits with leading research labs are possible (MPII Saarbrücken, Germany, Disney Research Zurich, Switzerland)
- Image recognition and machine learning in service robotics
- Information Extraction from Wikipedia and Other Web Sources
- Intelligent Inspection and Measuring of Cavities with a Cylindric Diameter and Prediction of the State Change
- Intelligent Methods for Mobile Forensics
- Mining Information From Stationary Cameras
- Research and development of computer vision algorithms.
- Focus on image and video from stationary surveillance cameras.
- Implementation of experimental prototypes.
- Design and development of application demonstrators.
- Model Transformations in Software Engineering
Tutor: Kočí Radek, Ing., Ph.D.
- Modelling of software systems for BigData processing
Currently, there are several well-established methods of distributed processing of BigData (e.g., batch processing by MapReduce, stream processing, various data distribution models for MPI, etc.). These methods utilize various patterns for data distribution and processing that affect design of BigData processing systems. Therefore, there is emerging need to apply, to combine, and to switch in runtime different data distribution and processing patterns in a BigData processing system without necessity to redesign or to rebuild the system. For example, we may need to optimize performance of a BigData processing system by making use of existing runtime monitoring data, which may eventually result into switching the data processing form often repeated batch processing to continuous stream processing. The objectives of this research are:
- To analyse state-of-the-art approaches of BigData distributed processing and to identify existing architectural and design patterns; to describe how these patterns emerge, transform, and affect each other in transition from high-level architectural design to low-level system design and in integration of system components defined in the system architecture.
- To propose an unified approach for modelling architecture and for design of BigData processing systems incorporating different patterns identified before; to utilize Model Driven Development (MDD, or MDE in general) in the approach, i.e., to define models and model transformations which can be used from an early design to implementation phase of BigData processing systems and which will allow to use different BigData processing patterns and their implementations (e.g., Apache Hadoop, Apache Storm, OpenMPI, etc.) including their combinations.
- To evaluate the approach on case studies.
The Ph.D. student will co-operate with other doctoral students and employees of the research group of information and database systems.
The full-time Ph.D. student will be involved in teaching according to needs of the department and the faculty.
The supervisor-specialist (consultant): RNDr. Marek Rychly, Ph.D.
- Modern Algorithms of Computer Graphics
The topic focuses algorithms of computer graphics and generally computer image synthesis. Its main goal is to research algorithms so that their features and application possibilities are better understood, so that they are deeply analyzed, so that they are improved or newly created, and so that they are efficiently implemented e.g. in CPU, in CPU with acceleration through SSE instructions, in embeded systems, in embedded systems with FPGA, or in other systems. Algorithms of interest include 3D model processing and acquisition. The programming work is expected in C, C++, C#, assembly language, CUDA, OpenCl, or VHDL. The algorithms of interest include:
- rendering using selected computer graphics methods (such as ray tracing, photon mapping, direct rendering of "point clouds", etc.),
- reconstruction of 3D scenes from images and/or video, eventually also fusing with other sensors, such as LIDAR,
- new algorithms of graphics and image synthesis suitable for mobile and embedded systems,
- modern algorithms of geometry suitable for applications in cpmputer graphics and perhaps also 3D printing,
- methods of video processing in the form of "cartoon", with false colours, with simulation of painterly techniques, etc.,
- emerging algorithms of 3D synthesis, holography, wavelet transform, frequency transform, etc.
After mutual agreement, individually selected algorithms can be considered as well as soon as they do belong to the general topic.
- Modern Methods of Language Generation
- Multi-scale model coupling in high performance computing.
- Neural Networks for Deep Learning
- New approaches to optimizations
- New technology for 3D hand geometry recognition
- New technology for 3D hand geometry recognition
- New technology for 3D hand geometry recognition
- New Versions of Automata and Grammars
- Non-traditional methods of image and video processing and acquisition
- Optimization of portofolio allocation cumulative risks
- Parallel Systems Programming
As you probably know, a compiler comprises from a language depending analytic part (front-end) which is producing a revised internal representation and a following part (back-end) which is generating a result object code or an assembler code.
The methodology for the front-end is already solved from the practical point of view many years and it is thought on a bachelor level of study. There are some generators of the analytical compiler part which are mainly based on the LALR grammars. These ones are able to generate the analytical part and a context depending part is easy built according to a known methodology. For some branches we use moreover the C/C++ language only. The front-end of such compiler is freely down able on the net. When we sufficiently design the internal representation, the front-end generator is depending on the input language only. Such internal representations are existing. The definition language pro the generator is mainly an attribute grammar.
Real practical problems occur in the back-end generation. An amount of processor architectures is high and moreover is permanently increasing in connection with mobile phones, and other embedded systems, Internet of Things, medical devices, automotive devices etc. One of the main reasons is a collision of using of available processors with already developed compilers and simultaneously large energy consumption. These designed devices cannot use such processors by reasons of energy consumption and often also of a license price. So, the number and variety of the processor architecture is quickly increasing. It will be sufficient to keep at disposition for the back-end a similar generating tool like for the front-end. In such way, we can to a great extend to speed-up a transport of applications (written mainly in the C language) on the new processors. The back-end generating is a relatively new topic which is not taught in the university curricula (at FIT as well).
One of the back-end problems is a parallel architectures programming. It means that the compiler is constructed in such way to be able to use instructions for parallel processing. The suitable language for such systems programming is OpenCL. The OpenCL (the Open Computing Language) is an industrial standard for a parallel programming of heterogeneous computer systems, e.g. personal computers equipped by GRP (graphics), APU, possibly DSP (audio). What we can link to?
In a frame of the Lissom group research, a reconfigurable C compiler grew. It is now a part of the Codasip Studio of the Codasip Ltd. (www.codasip.com) and also for our university. We have some experience with this research. It is sure, that we do a research on the world level which is practically requested and which is not definitely solved. There are definition languages, the internal representation, and the reconfigurable C compiler. We have developed a workable generator, but it is not sure, whether it is sufficiently effective for sufficient scale of architectures.
The goal of this thesis is research and development of an OpenCL compiler that exploits paralellism specified in OpenCL and targets mainly architectures with SIMD instructions, and VLIW and multi-threaded architectures.
More information verbally.
Possible engagement in paid activities:
-a basic stipendium of the PhD. program
-an remuneration from grant projects
-local
-European
-some part time job in the co-operating company
-possible to pass an internship program
Contact and information
Prof. Ing. Tomáš Hruška, CSc. - hruska@fit.vutbr.cz - Process modeling in Information Systems
This subject comes from the longtime prof. Hruškas research in an area of process models which was performed together with PhD. students in the last years. A fundament of this research is a processes analysis with the target to optimize them. The research runs in two branches:
1. A workflow models, their analysis a a ways to the business process optimization
2. Process mining
The first one works with a classification of the proper workflow models, their standards a techniques of a discrete modelling. The goal is to find the workflow process modeling method with the usage modern programming languages, possibly with a possibility of an object-oriented approach application. Moreover is possible to optimize this method a compare it with existing standards and systems in the area of a workflow model description. This topic is solved in the frame of the TIP grant Workflow System as a powerful tools for Business process reengineering.
The second area of process mining is focused to a detection, analysis a optimization of business models based on dates for log files. This analysis is representing a currently missing connection between a classical business process analysis and a data mining.
The main goals are following:
Information systems are optimizing a process management by their definition, supplying of relevant information about a product an about new generated requests. We try to design and implement an information system for a modelling, management and following business process optimization. The goal is to automatize an information handover between particular sources and to make sure that business rules and security is kept. The resulting system will provide an effective information flow management.
More information verbally.
Possible engagement in paid activities:- a basic stipendium of the PhD. program
- an remuneration from grant projects
- local
- European
- some part time job in the co-operating company
- possible to pass an internship program
Contact and information
Prof. Ing. Tomáš Hruška, CSc. - hruska@fit.vutbr.cz
- Profile-guided Compiler Optimizations
As you probably know, a compiler comprises from a language depending analytic part (front-end) which is producing a revised internal representation and a following part (back-end) which is generating a result object code or an assembler code.
The methodology for the front-end is already solved from the practical point of view many years and it is thought on a bachelor level of study. There are some generators of the analytical compiler part which are mainly based on the LALR grammars. These ones are able to generate the analytical part and a context depending part is easy built according to a known methodology. For some branches we use moreover the C/C++ language only. The front-end of such compiler is freely down able on the net. When we sufficiently design the internal representation, the front-end generator is depending on the input language only. Such internal representations are existing. The definition language pro the generator is mainly an attribute grammar.
Real practical problems occur in the back-end generation. An amount of processor architectures is high and moreover is permanently increasing in connection with mobile phones, and other embedded systems, Internet of Things, medical devices, automotive devices etc. One of the main reasons is a collision of using of available processors with already developed compilers and simultaneously large energy consumption. These designed devices cannot use such processors by reasons of energy consumption and often also of a license price. So, the number and variety of the processor architecture is quickly increasing. It will be sufficient to keep at disposition for the back-end a similar generating tool like for the front-end. In such way, we can to a great extend to speed-up a transport of applications (written mainly in the C language) on the new processors. The back-end generating is a relatively new topic which is not taught in the university curricula (at FIT as well).In the back-end, a static analysis is running during a compilation. It make possible to generate a currenty optimal code which is based on information available during the compilation. But this approach is not sufficient for some architectures. Especially in the case when the number of application program sis limited (a frequent situation for more processors), it is necessary to use for the optimization also data reached after the program execution (a profil).
What we can link to?
In a frame of the Lissom group research, a reconfigurable C compiler grew. It is now a part of the Codasip Studio of the Codasip Ltd. (www.codasip.com) and also for our university. We have some experience with this research. It is sure, that we do a research on the world level which is practically requested and which is not definitely solved. There are definition languages, the internal representation, and the reconfigurable C compiler. We have developed a workable generator, but it is not sure, whether it is sufficiently effective for sufficient scale of architectures.
The goal of this thesis is a research and development of profile-guided optimizations in the C and C++ language compiler. Static analyses in compilers are not able to provide information sufficiently precise for optimizations, but using a profile allows to greatly improve the generated code quality.
More information verbally.
Possible engagement in paid activities:
-basic stipendium of the PhD. program
-an remuneration from grant projects
-local
-european
-some part time job in the co-operating company
-possible to pass an internship program
Contact and information
Prof. Ing. Tomáš Hruška, CSc. -hruska@fit.vutbr.cz - Prototyping of sensor systems by multiagent systems
- Quality Management Model
- Real Robots Planning Algorithms
- Reconstruction of damaged surfaces of CD/DVD/BR/HDD for forensic purposes
- Regular Expression Matching in High-Speed Networks
- Regular Expression Matching in High-Speed Networks
- Regular Expression Matching in High-Speed Networks
- Regulated automata and grammars
- Research of Intrusion Detection Systems for Embedded and Mobile Devices
Tutor: Hanáček Petr, doc. Dr. Ing.
- Research of Intrusion Detection Systems for Embedded and Mobile Devices
Tutor: Hanáček Petr, doc. Dr. Ing.
- Research of Intrusion Detection Systems for Embedded and Mobile Devices
Tutor: Hanáček Petr, doc. Dr. Ing.
- Risk Management Methods in Projects Management
- Rouhg Sets
- Search in speech using querying by example
Tutor: Černocký Jan, prof. Dr. Ing.
- Search in speech using querying by example
Tutor: Černocký Jan, prof. Dr. Ing.
- Search in speech using querying by example
Tutor: Černocký Jan, prof. Dr. Ing.
- Secure and Dependable Software-Defined Networks
- Semantic web portal generator
- Scheduling and Synchronization for Multi-Core Platforms
Multi-core solutions represent a trend in recent computational architectures and applications, primarily due to the power and thermal limitations of technology scaling. From an application perspective, it is necessary to leverage parallelism and to limit synchronization using appropriate scheduling mechanisms over available cores to meet application-specific constraints related e.g. to power consumption, quality of services they deliver, performance, dependability or timeliness of their reactions. The aim of the project is:
- to analyze the actual state in the area of multi-core architectures and design styles of programs (user applications and their control layers based on "conventional" operating systems such as Android / Linux, Windows, iOS or specialized ones such as uC/OS-II or FreeRTOS) running over them,
- to identify actual problems in terms of scalabilty of multi-core architectures as well as programs going to be executed by the architectures,
- to propose a method for increasing scalability of multi-core architectures and/or programs they are designed to execute,
- to evaluate an impact of the method to scalability.
The project can be oriented into various directions such as multi-core system design optimization, autonomously adaptive / reconfigurable systems, task / communication scheduling or operating system architectures for multi-core systems. During the project, "conventional" multi-core platforms such as ARM Cortex-A9, Intel/AMD or specialized ones such as Xilinx Zynq 7000, Altera SoC FPGA or Microsemi Smartfusion2 can be utilized to check the proposed method in practice.
Tutor: Strnadel Josef, Ing., Ph.D.
- Software Defined Networking Aware of Application, User and Service Demands
- Static Analysis of Heap-Manipulating Programs
- Static Analysis of Heap-Manipulating Programs
- Static Analysis of Heap-Manipulating Programs
- System for the detection and recovery of transient faults in FPGA based systems
- Systems of Formal Models
- Testing Methods for Security Products
Tutor: Hanáček Petr, doc. Dr. Ing.
- The possibilities of using time redundancy during the design of fault tolerant systems
- Visual Geo-Localization on Mobile Devices
The project deals with geo-localization of mobile devices in unknown environments using computer vision and computer graphics methods. The aim is to investigate and develop new image registration techniques (with geo-localized image database or 3D terrain model). The goal is an efficient implementation of proposed methods on mobile devices as well as search for additional applications in the area of image processing, computational photography, and augmented reality.
- Further information: http://cadik.posvete.cz/locate/
- Contact: http://cadik.posvete.cz/
- Cooperation and research visits with leading research labs are possible (MPII Saarbrücken, Germany, Disney Research Zurich, Switzerland, INRIA Bordeaux, France)
Course structure diagram with ECTS credits
Abbreviation | Title | L. | Cr. | Com. | Compl. | Hr. range | Gr. | Op. |
---|---|---|---|---|---|---|---|---|
JAD | Ph.D. Test of English | cs, en | 0 | Compulsory | Ex | yes |
Abbreviation | Title | L. | Cr. | Com. | Compl. | Hr. range | Gr. | Op. |
---|---|---|---|---|---|---|---|---|
JAD | Ph.D. Test of English | cs, en | 0 | Compulsory | Ex | yes |
Abbreviation | Title | L. | Cr. | Com. | Compl. | Hr. range | Gr. | Op. |
---|---|---|---|---|---|---|---|---|
JA6D | English for PhD Students | cs, en | 0 | Elective | Ex | P - 13 / COZ - 13 | yes | |
PDD | Applications of Parallel Computers | cs, en | 0 | Elective | Ex | P - 39 | yes | |
IV108 | Bioinformatics | cs, en | 0 | Elective | Ex | P - 13 / COZ - 13 | yes | |
FAD | Formal Program Analysis | cs, en | 0 | Elective | Ex | P - 26 | yes | |
MSD | Modelling and Simulation | cs, en | 0 | Elective | Ex | P - 39 / Cp - 9 | yes | |
MMD | Advanced Methods of 3D Scene Visualisation | cs, en | 0 | Elective | Ex | P - 39 | yes | |
MZD | Modern Methods of Speech Processing | cs, en | 0 | Elective | Ex | P - 39 | yes | |
TID | Modern Theoretical Computer Science | cs, en | 0 | Elective | Ex | P - 39 / PR - 13 | yes | |
OPD | Optics | cs, en | 0 | Elective | Ex | P - 39 / PR - 13 | yes | |
ORID | Optimal Control and Identification | cs, en | 0 | Elective | Ex | P - 26 / PR - 13 | yes | |
PGD | Computer Graphics | cs, en | 0 | Elective | Ex | P - 39 | yes | |
PBD | Advanced biometric systems | cs, en | 0 | Elective | Ex | P - 26 / PR - 4 | yes | |
PTD | The Principles of Testable Design Synthesis | cs, en | 0 | Elective | Ex | P - 39 | yes | |
SVD | Specification of Embedded Systems | cs | 0 | Elective | Ex | P - 39 | yes | |
DMA1 | Statistics, Stochastic Procesess, Operational Analysis | cs | 0 | Elective | Ex | P - 39 | yes | |
TKD | Category Theory | cs, en | 0 | Elective | Ex | P - 26 | yes | |
TJD | Programming Language Theory | cs, en | 0 | Elective | Ex | P - 39 | yes | |
APD | Selected Topics on Language Parsing and Translation | cs, en | 0 | Elective | Ex | P - 39 / PR - 13 | yes | |
ZZD | Knowledge Discovery in Databases | cs, en | 0 | Elective | Ex | P - 39 / PR - 13 | yes | |
DBM1 | Advanced Methods of Processing and Analysis of Images | cs, en | 0 | Elective | Ex | P - 39 | yes | |
ZPD | Natural Language Processing | cs, en | 0 | Elective | Ex | P - 39 | yes | |
ASD | Audio and Speech Processing by Humans and Machines | cs, en | 0 | Elective | Ex | P - 39 | yes |
Abbreviation | Title | L. | Cr. | Com. | Compl. | Hr. range | Gr. | Op. |
---|---|---|---|---|---|---|---|---|
BID | Information System Security and Cryptography | cs, en | 0 | Elective | Ex | P - 39 / PR - 4 | yes | |
DMA2 | Discrete Processes in Electrical Engineering | cs | 0 | Elective | Ex | P - 39 | yes | |
EUD | Evolutionary and Unconventional Hardware | cs, en | 0 | Elective | Ex | P - 26 | yes | |
EVD | Evolutionary Computation | cs, en | 0 | Elective | Ex | P - 39 | yes | |
SSD | Formal Specifications of Computer-Based Systems | cs | 0 | Elective | Ex | P - 39 | yes | |
ISD | Intelligent Systems | cs, en | 0 | Elective | Ex | P - 26 / PR - 26 | yes | |
KRD | Classification and recognition | cs, en | 0 | Elective | Ex | P - 39 | yes | |
MLD | Mathematical Logic | cs, en | 0 | Elective | Ex | P - 26 | yes | |
MID | Modern Mathematical Methods in Informatics | cs, en | 0 | Elective | Ex | P - 26 | yes | |
DTK1 | Modern Network Technologies | cs | 0 | Elective | Ex | P - 39 | yes | |
NVD | Embedded Systems Design | cs | 0 | Elective | Ex | P - 26 | yes | |
QB4 | Neural Networks, Adaptive and Optimum Filtering | cs | 0 | Elective | Ex | P - 39 | yes | |
SOD | Fault Tolerant Systems | cs, en | 0 | Elective | Ex | P - 39 | yes | |
TAD | Theory and Applications of Petri Nets | cs, en | 0 | Elective | Ex | P - 39 / Cp - 8 | yes | |
PFTD | Theory of Financial Markets | cs, en | 0 | Elective | Ex | P - 26 / COZ - 20 | yes | |
VKD | Selected Chapters on Algorithms | cs, en | 0 | Elective | Ex | P - 39 | yes | |
VPD | Selected Topics of Information Systems | cs, en | 0 | Elective | Ex | P - 39 | yes | |
SID | Selected Topics of Software Engineering and Database Systems | cs, en | 0 | Elective | Ex | P - 39 / PR - 13 | yes | |
VND | Higly Sophisticated Computations | cs, en | 0 | Elective | Ex | P - 39 / Cp - 26 | yes |